The present invention relates to solid-state imaging apparatus, and more particularly relates to a solid-state imaging apparatus capable of reducing power consumption.
A description will be given below first by way of FIGS. 1, 2, and 3 with respect to fundamental construction and drive method of a general MOS-type solid-state imaging apparatus. FIG. 1 shows a general pixel construction used in MOS solid state imaging devices. What is denoted by numeral 100 is a unit pixel, and a plurality of unit pixels is arranged into a two-dimensional matrix to acquire image information. Shown respectively are: 101, a photodiode for effecting photoelectric conversion; 104, an amplification transistor for amplifying and reading light-generated electric charge occurring at the photodiode 101 by converting it into voltage for example by means of pn junction capacitor or gate capacitor; 102, a transfer transistor for transferring light-generated electric charge occurring at the photodiode 101 to gate terminal of the amplification transistor 104; 103, a reset transistor for resetting the gate terminal of amplification transistor 104 and the photodiode 101; and 105, a select transistor for selecting the pixel to transmit an output of the amplification transistor 104 to a vertical signal line 110.
These components but the photodiode 101 are shielded from light.
Denoted by 106 is a pixel power supply line, which is to supply a power supply voltage in common to all pixels, and is electrically connected to drain terminal of the amplification transistor 104 and drain terminal of the reset transistor 103. 107 is a row reset line for resetting pixels corresponding to one row, which is electrically connected respectively to the gate terminals of reset transistor 103 of pixels corresponding to one row. 108 is a row transfer line for transferring the light-generated electric charge of the pixels corresponding to one row to the gate terminal of amplification transistor 104 of each pixel, which is electrically connected respectively to the gate terminals of transfer transistor 102 of the pixels corresponding to one row. 109 is a row select line for selecting pixels corresponding to one row, which is electrically connected respectively to the gate terminals of select transistor 105 of the pixels corresponding to one row. With such pixel construction, a photoelectric conversion function, reset function, memory function, amplification/read function, and select function are achieved.
FIG. 2 typically shows a general fundamental construction of MOS solid-state imaging apparatus. 200 denotes a pixel section where unit pixels 100 are arranged into a two-dimensional matrix which corresponds to pixels P11 to P33. Here, for ease of explanation, the pixel section 200 is shown as 3 rows by 3 columns of unit pixels 100. 202 denotes a vertical scanning circuit section for selecting row, which sequentially outputs vertical scanning pulse φV-i (i=1, 2, 3). 203 denotes a vertical select switch section, which transmits row select pulse φSEL, row reset pulse φRS, and row transfer pulse φTX respectively to the row select line 109, row reset line 107, and row transfer line 108 of each pixel P11 to P33 in accordance with the vertical scanning pulse φV-i. While, in FIG. 2, only one line is shown as the lines for transmitting to each row the row select pulse φSEL, row reset pulse φRS, and row transfer pulse φTX, and only one unit of vertical select switch (MV-1, MV-2, MV-3) for each row is shown, these are provided respectively separately from each other.
201 denotes a current supply section where current supplies ML1, ML2, and ML3 provided for each column are respectively electrically connected to the vertical signal line 110 as described in FIG. 1. A source follower circuit is thereby formed for each column by the amplification transistor 104 and current supply ML1 to ML3. Here, the current supply ML1 to ML3 is provided with a function for causing a flow of constant bias current. 204 denotes a column processing circuit section where correlated double sampling (CDS) respectively of the pixel signals outputted from the above described source follower circuits is performed by column processing circuits CDS1, CDS2, CDS3 provided for each column. The column processing circuit CDS1 to CDS3 of each column performs signal processing such as elimination of offset variance for example of fixed-pattern noise of pixel and then stores result of the signal processing to a memory.
205 denotes a horizontal scanning circuit section for selecting column, which is to sequentially output horizontal scanning pulse φH-j (j=1, 2, 3). 206 denotes a horizontal select switch section where the signal processing result stored at the column processing circuit section 204 is transmitted to a horizontal signal line 207 in accordance with the horizontal scanning pulses φH-j. 208 denotes an amplifier for amplifying the signal processing result stored at the column processing circuit section 204 and transmitted to the horizontal signal line 207 and for outputting it to an external system.
A general drive timing of the MOS solid-state imaging apparatus having such construction will now be described by way of a timing chart shown in FIG. 3. When vertical scanning pulse φV-1 of the first row is outputted (or is driven to H level) from the vertical scanning circuit section 202, the pixels of the first row become drivable. More particularly, for the pixels of the first row: the row select pulse φSEL becomes transmittable as φSEL-1 to gate terminal of the select transistor 105 of the pixels of the first row through the vertical select switch MV-1 and row select line 109; row reset pulse φRS becomes transmittable as φRS-1 to gate terminal of the reset transistor 103 of the pixels of the first row through the vertical switch MV-1 and row reset line 107; and row transfer pulse φTX becomes transmittable as φTX-1 to gate terminal of the transfer transistor 102 of the pixels of the first row through the vertical switch MV-1 and row transfer line 108.
An operation during period Tv will now be described. First, when the vertical scanning pulse φV-1 is driven to “H” level and then row select pulse φSEL-1 to “H” level, an output of the amplification transistor 104 becomes transmittable to the vertical signal line 110. In other words, a period for reading signal and processing signal is started. Next, when the row reset pulse φRS-1 is driven to “H” level, the gate terminal of the amplification transistor 104 is reset to the level of a pixel power supply VDD. Next, the row reset pulse φRS-1 is brought to “L” level, and a reset level output outputted from the amplification transistor 104 at this time is sampled at the column processing circuit section 204.
Next, the row transfer pulse φTX-1 is driven to “H” level to transfer a light-generated electric charge accumulated at photodiode 101 to the gate terminal of the amplification transistor 104. Next, the row transfer pulse φTX-1 is brought to “L” level so as to sample again the signal level output outputted at this time at the column processing circuit section 204.
At this time, since the output of the amplification transistor 104 charges a parasitic capacitance of the vertical signal line 110 and an input capacitance of the column processing circuit section 204, a certain charging period becomes necessary for the vertical signal line 110 to attain signal level of the output of the amplification transistor 104. The charging period depends on bias current of the current supply ML1 to ML3, and becomes shorter with an increase in the bias current. The bias current is usually set to a sufficiently large value so that a signal level at the time of saturation of photodiode 101 is obtained within the period Tv.
Subsequently, a differential processing between the sampled signal level output and reset level output is performed at the column processing circuit section 204, and signals after the differential processing are respectively stored to the column processing circuits CDS1, CDS2, and CDS3. The row select signal φSEL-1 is then brought to “L” level to end the period for reading signal and processing signal. The row reset pulse φRS-1 and row transfer pulse φTX-1 are then driven to “H” level to reset the photodiode 101, and an accumulation of light-generated electric charge is subsequently started at the photodiode 101.
An operation during period Th will now be described.
When horizontal scanning pulses φH-1, φH-2, and φH-3 are sequentially outputted from the horizontal scanning circuit section 205, the signals after the differential processing stored at the column processing circuits CDS1, CDS2, and CDS3 of the column processing circuit section 204 are sequentially read out to the horizontal signal line 207 respectively through the horizontal select switches MH1, MH2, and MH3 of the horizontal select switch section 206. The signals read out to the horizontal signal line 207 are amplified at the output amplifier section 208 and are outputted to the outside system. The signal to be outputted to the outside system is indicated by Vout in FIG. 3. At this time, a suitable bias current corresponding to a signal band is supplied to the output amplifier section 208.
With the operation of the above, pixels P11, P12, and P13 corresponding to one row are read out. By sequentially performing this operation from the first row through the third row, signals of all pixels of the pixel section 200 can be read out. In particular, the pixel signals of pixels P11 to P33 of the light-receiving pixel section 200 are sequentially outputted as Vout from the output amplifier section 208. The above period is one frame period Tf and, in this description, is an accumulation period of light-generated electric charge of photodiode 101.